Flip chip is a process in which a semiconductor Si chip is flipped over so that the connection pads face towards the substrate (laminate). In the conventional flip chip bonding, ceramic carriers, typically alumina, have been used in combination with solder as the laminate. However, the need for high-density interconnects in cost-effective flip chip packaging has been a motivation for using organic laminates. In contrast to ceramic substrates, organic laminates have better electrical performance at lower cost. However, when organic laminates are used for the flip chip assembly, laminate bending and warpage can occur due to a thermal mismatch between materials, e.g., organic laminate and chip. The bending and warpage can increase as the size of the organic laminate increases for high performance chips and components, and as the thickness of the organic laminate decreases, for example in coreless laminates.
For high performance flip chip applications, Cu low-k dielectric layers are widely used in the Back-End-of-Line (BEOL) structure of Si chips to reduce capacitance in the interconnect layers. In recent applications of flip chips, ultra low-k dielectric materials are used for lower capacitance. These materials are more fragile than traditional BEOL dielectrics and more susceptible to damage during assembly.
During the flip chip assembly process, the Si chip and the organic laminates experience a temperature cycle from room temperature to the melting temperature of solder materials back to room temperature during cool down. The coefficient of thermal expansion (CTE) mismatch between a Si chip and an organic laminate creates thermally-induced stress/strain in the flip-chip structure during the flip chip assembly process.
The thermally-induced stress/strain in the flip-chip structure often results in a failure of the BEOL structure such as, for example, cracking or delamination. This failure is becoming more common because of the fragility of low-k dielectric layers. This thermally-induced stress/strain can become even more problematic with the use of lead-free solders.
More specifically, due to the thermal expansion mismatch between organic laminates (approximately 17×10−6/C) and silicon chips (approximately 2.6×10−6/C), there are stresses produced during cool-down of the modules from the chip join temperature. In a die with fragile low-k dielectric materials in the BEOL, coupled with lead-free bump metallurgies which are higher modulus than leaded bumps, the result is ultra-low dielectric constant (ULK) cracking on cool-down, i.e., “white bumps” observed by CSAM (Scanning Acoustic Microscopy in C mode). “White bumps”/ULK cracking is a very serious problem which needs to be resolved in order to successfully implement lead-free bump technology on organic packages for 45 nm and 32 nm silicon technology nodes, and beyond. This phenomenon is not observed when joining the same die to glass-ceramic modules, which are CTE-matched to silicon, and this phenomenon is not observed when using leaded bumps on organic packages, due to the lower yield stress of the high-lead bumps imparting less stress to the system.
There are several approaches available to mitigate white bumps, including the use of slower cool-down rates during chip join, use of less silver content in the lead-free Cu—Ag alloy. However, these approaches have issues. For example, the slow cool-down rates required to totally alleviate white bumps are non-manufacturable due to excessive time and/or need for impractically long belt furnaces. The use of less silver in the lead-free alloy may not be easily implemented due to electrical requirements.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.